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FINAL
COM'L: -12/15/20
MACH445-12/15/20
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
s 100-pin version of the MACH435 in PQFP s 5 V, in-circuit programmable s JTAG, IEEE 1149.1 JTAG testing capability s 128 macrocells s 12 ns tPD s 83 MHz fCNT s 70 inputs with pull-up resistors s 64 outputs s 192 flip-flops -- 128 macrocell flip-flops -- 64 input flip-flops
Lattice Semiconductor
s Up to 20 product terms per function, with XOR s Flexible clocking -- Four global clock pins with selectable edges -- Asynchronous mode available for each macrocell s 8 "PAL33V16" blocks s Input and output switch matrices for high routability s Fixed, predictable, deterministic delays s JEDEC-file compatible with MACH435 s Zero-hold-time input register option
GENERAL DESCRIPTION
The MACH445 is a member of the high-performance EE CMOS MACH 4 family. This device has approximately twelve times the macrocell capability of the popular PAL22V10, with significant density and functional features that the PAL22V10 does not provide. It is architecturally identical to the MACH435, with the addition of JTAG and 5-V programming features. The MACH445 consists of eight PAL blocks interconnected by a programmable central switch matrix. The central switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. Routability is further enhanced by an input switch matrix and an output switch matrix. The input switch matrix provides input signals with alternative paths into the central switch matrix; the output switch matrix provides flexibility in assigning macrocells to I/O pins. The MACH445 has macrocells that can be configured as synchronous or asynchronous. This allows designers to implement both synchronous and asynchronous logic together on the same device. The two types of design can be mixed in any proportion, since the selection on each macrocell affects only that macrocell. Up to 20 product terms per function can be assigned. It is possible to allocate some product terms away from a macrocell without losing the use of that macrocell for logic generation. The MACH445 macrocell provides either registered or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type, T-type, J-K, or S-R to help reduce the number of product terms used. The flip-flop can also be configured as a latch. The register type decision can be made by the designer or by the software. All macrocells can be connected to an I/O cell through the output switch matrix. The output switch matrix makes it possible to make significant design changes while minimizing the risk of pinout changes.
Publication# 17468 Rev. E Issue Date: May 1995
Amendment /0
2
Block A I/O0-I/O7 I/O8-I/O15 I/O16-I/O23 I/O24-I/031 Block B Block C Block D 8 8 I/O Cells 4 8 4 16 Macrocells OE 16 Output Switch Matrix 8 I/O Cells 8 4 8 16 16 Macrocells OE OE 16 4 16 Macrocells 4 16 16 16 4 16 Output Switch Matrix 8 Output Switch Matrix 4 Output Switch Matrix 16 16 16 Macrocells 16 Input Switch Matrix Input Switch Matrix Input Switch Matrix 4 66 X 90 AND Logic Array and Logic Allocator 24 33 24 33 66 X 90 AND Logic Array and Logic Allocator 4 8 8 I/O Cells I/O Cells 8 8 Clock Generator Clock Generator Clock Generator 16 16 Input Switch Matrix 66 X 90 AND Logic Array and Logic Allocator 33 24 33 24 I2, I5
BLOCK DIAGRAM
4
4
Clock Generator
8
4
OE
66 X 90 AND Logic Array and Logic Allocator
4 33 24 33 24 33
Central Switch Matrix
24 33 24
CLK0/I0, CLK1/I1, CLK2/I3, CLK3/I4
MACH445-12/15/20
Input Switch Matrix Input Switch Matrix 4 OE 66 X 90 AND Logic Array and Logic Allocator 4 OE 16 Macrocells 16 16 Output Switch Matrix 8 I/O Cells 8 4 8 I/O Cells 8 16 8 Output Switch Matrix 4 16 16 16 4 8 4 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 16 Output Switch Matrix 8 I/O Cells 8 16 16 Macrocells Clock Generator Clock Generator I/O48-I/O55 Block G I/O40-I/O47 Block F Block H
4
2
Input Switch Matrix
Input Switch Matrix
4
66 X 90 AND Logic Array and Logic Allocator
4 OE
66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 4 8 4
4
Clock Generator
Clock Generator
4
OE
16 16 Output Switch Matrix 8 I/O Cells 8 16
8
17468E-1
I/O56-I/O63
I/O32-I/O39 Block E
CONNECTION DIAGRAM MACH445 (MACH435) Top View PQFP
BLOCK A BLOCK H I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC GND GND VCC I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56
(10) 100 (9) 99 (8) 98 (7) 97 (6) 96 (5) 95 (4) 94 (3) 93
I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 VCC GND GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39
31 (33) 32 (34) 33 (35) 34 (36) 35 (37) 36 (38) 37 (39) 38 (40) 39 40 41 42 43 (45) 44 (46) 45 (47) 46 (48) 47 (49) 48 (50) 49 (51) 50 (52)
GND GND TDI I5 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I0/CLK0 VCC VCC GND GND I1/CLK1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 TMS TCK GND GND
1 2 3 4 (83) 5 (12) 6 (13) 7 (14) 8 (15) 9 (16) 10 (17) 11 (18) 12 (19) 13 (20) 14 15 16 17 18 (23) 19 (24) 20 (25) 21 (26) 22 (27) 23 (28) 24 (29) 25 (30) 26 (31) 27 28 29 30
(82) (81) (80) (79) (78) (77) (76) (75)
92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
(73) (72) (71) (70) (69) (68) (67) (66) (65)
(62) (61) (60) (59) (58) (57) (56) (55) (54) (41)
GND GND TD0 TRST* I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 I4/CLK3 GND GND VCC VCC I3/CLK2 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 I2 ENABLE* GND GND
BLOCK B
BLOCK C
BLOCK D
BLOCK E
PIN DESIGNATIONS
CLK/I GND I I/O VCC = = = = = Clock or Input Ground Input Input/Output Supply Voltage
MACH445-12/15/20
BLOCK F
17468E-2
BLOCK G
3
ORDERING INFORMATION Commercial Products
Programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of:
MACH 445 -12
Y
C
FAMILY TYPE MACH = Macro Array CMOS High-Speed
OPTIONAL PROCESSING Blank = Shipped in Trays
DEVICE NUMBER 445 = 2nd Generation, 128 Macrocells, 100 Pins
OPERATING CONDITIONS C = Commercial (0C to +70C)
SPEED -12 = 12 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD
PACKAGE TYPE Y = 100-Pin Plastic Quad Flat Pack (PQR100)
Valid Combinations MACH445-12 MACH445-15 MACH445-20 YC
Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
4
MACH445-12/15/20
FUNCTIONAL DESCRIPTION
The MACH445 consists of eight PAL blocks connected by a central switch matrix. There are 64 I/O pins and 6 dedicated input pins feeding the central switch matrix. These signals are distributed to the eight PAL blocks for efficient design implementation. There are 4 global clock pins that can also be used as dedicated inputs. All inputs and I/O pins have built-in pull-up resistors. While it is always good design practice to tie unused pins high, the pull-up resistors provide design security and stability in the event that unused pins are left disconnected.
The Clock Generator
Each PAL block has a clock generator that can generate four clock signals for use throughout the PAL block. These four signals are available to all macrocells and I/O cells in the PAL block, whether in synchronous or asynchronous mode. The clock generator chooses the four signals from the eight possible signals given by the true and complement versions of the four global clock pin signals.
The Product-Term Array
The MACH445 product-term array consists of 80 product terms for logic use, eight product terms for output enable use, and two product terms for global PAL block initialization. Each macrocell has a nominal allocation of 5 product terms for logic, although the logic allocator allows for logic redistribution. Each I/O pin has its own individual output enable term. The initialization product terms provide asynchronous reset or preset to synchronous-mode macrocells in the PAL block.
The PAL Blocks
Each PAL block in the MACH445 (Figure 1) contains a clock generator, a 90-product-term logic array, a logic allocator, 16 macrocells, an output switch matrix, 8 I/O cells, and an input switch matrix. The central switch matrix feeds each PAL block with 33 inputs. This makes the PAL block look effectively like an independent "PAL33V16" with 8 to 16 buried macrocells. In addition to the logic product terms, individual output enable product terms and two PAL block initialization product terms are provided. Each I/O pin can be individually enabled. All flip-flops that are in the synchronous mode within a PAL block are initialized together by either of the PAL block nitialization product terms.
The Logic Allocator
The logic allocator in the MACH445 takes the 80 logic product terms and allocates them to the 16 macrocells as needed. Each macrocell can be driven by up to 20 product terms in synchronous mode, or 18 product terms in asynchronous mode. When product terms are routed away from a macrocell, all 5 product terms may be redirected, which precludes the use of the macrocell for logic generation. It is possible to redirect only 4 product terms, leaving one for simple function generation. The design software automatically configures the logic allocator when fitting the design into the device. The logic allocator also provides an exclusive-OR gate. This gate allows generation of combinatorial exclusiveOR logic, such as comparison or addition. It allows registered exclusive-OR functions, such as CRC generation, to be implemented more efficiently. Emulating all flip-flop types with a D-type flip-flop is also made possible. Register type emulation is automatically handled by the design software. Table 1 illustrates which product term clusters are available to each macrocell within a PAL block. Refer to Figure 1 for cluster and macrocell numbers.
The Central Switch Matrix and Input Switch Matrix
The MACH445 central switch matrix is fed by the input switch matrices in each PAL block. Each PAL block provides 16 internal feedback signals, 8 registered input signals, and 8 I/O pin signals to the input switch matrix. Of these 32 signals, 24 decoded signals are provided to the central switch matrix by the input switch matrix. The central switch matrix distributes these signals back to the PAL blocks in a very efficient manner that provides for high performance. The design software automatically configures the input and central switch matrices when fitting a design into the device.
MACH445-12/15/20
5
Table 9. Logic Allocation
Macrocell M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 Available Clusters C0, C1, C2 C0, C1, C2, C3 C1, C2, C3, C4 C2, C3, C4, C5 C3, C4, C5, C6 C4, C5, C6, C7 C5, C6, C7, C8 C6, C7, C8, C9 C7, C8, C9, C10 C8, C9, C10, C11 C9, C10, C11, C12 C10, C11, C12, C13 C11, C12, C13, C14 C12, C13, C14, C15 C13, C14, C15 C14, C15
The macrocells can be configured as registered, latched, or combinatorial. In combination with the logic allocator, the registered configuration can be any of the standard flip-flop types. The macrocell provides internal feedback whether configured with or without the flipflop, and whether or not the macrocell drives an I/O cell. The flip-flop clock depends on the mode selected for the macrocell. In synchronous mode, any of the PAL block clocks generated by the Clock Generator can be used. In asynchronous mode, the additional choice of either edge of an individual product-term clock is available. Initialization can be handled as part of a bank of macrocells via the PAL block initialization terms if in synchronous mode, or individually if in asynchronous mode. In synchronous mode, one of the PAL block product terms is available each for preset and reset. The swap function determines which product term drives which function. This allows initialization polarity compatibility with the MACH 1 and 2 series. In asynchronous mode, one product term can be used either to drive reset or preset.
The Macrocell and Output Switch Matrix
The MACH445 has 16 macrocells, half of which can drive I/O pins; this selection is made by the output switch matrix. Each macrocell can drive one of four I/O cells. The allowed combinations are shown in Table 2. Please refer to Figure 1 for macrocell and I/O pin numbers. Table 2. Output Switch Matrix Combinations
Macrocell M0, M1 M2, M3 M4, M5 M6, M7 M8, M9 M10, M11 M12, M13 M14, M15 I/O Pin I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Routable to I/O Pins I/O5, I/O6, I/O7, I/O0 I/O6, I/O7, I/O0, I/O1 I/O7, I/O0, I/O1, I/O2 I/O0, I/O1, I/O2, I/O3 I/O1, I/O2, I/O3, I/O4 I/O2, I/O3, I/O4, I/O5 I/O3, I/O4, I/O5, I/O6 I/O4, I/O5, I/O6, I/O7 Available Macrocells M0, M1, M2, M3, M4, M5, M6, M7 M2, M3, M4, M5, M6, M7, M8, M9 M4, M5, M6, M7, M8, M9, M10, M11 M6, M7, M8, M9, M10, M11, M12, M13 M8, M9, M10, M11, M12, M13, M14, M15 M10, M11, M12, M13, M14, M15, M0, M1 M12, M13, M14, M15, M0, M1, M2, M3 M14, M15, M0, M1, M2, M3, M4, M5
The I/O Cell
The I/O cell in the MACH445 consists of a three-state buffer and an input flip-flop. The I/O cell is driven by one of the macrocells, as selected by the output switch matrix. Each I/O cell can take its input from one of eight macrocells. The three-state buffer is controlled by an individual product term. The input flip-flop can be configured as a register or latch. Both the direct I/O signal and the registered/latched signal are available to the input switch matrix, and can be used simultaneously if desired.
JTAG Testing
JTAG is the commonly used acronym for the IEEE Standard 1149.1-1990. The JTAG standard defines input and output pins, logic control functions, and instructions. Lattice/Vantis has incorporated this standard into the MACH445 device. The JTAG standard was developed as a means of providing both board-level and device-level testing.
6
MACH445-12/15/20
Five-Volt Programming
Another benefit from the JTAG circuitry that we have derived is the ability to use the JTAG port for five-volt programming. This allows the device to be soldered to the board before programming. Once the device is attached, the delicate Plastic Quad Flat Pack, or PQFP, leads are protected from programming and testing operations that could potentially damage them. Programming and verification of the device is done serially which is ideal for on-board programming since it only requires the use of the Test Access Port. Use of the programming Enable Pin (ENABLE*) is optional.
Zero-Hold-Time Input Register
The MACH445 device has a zero-hold time (ZHT) fuse. This fuse controls the time delay associated with loading data into all I/O cell registers and latches in the MACH445 device. When programmed, the ZHT fuse increases the data path setup delays to input storage elements, matching equivalent delays in the clock path. When the fuse is erased, the setup time to the input storage element is minimized and the device timing is compatible with the MACH435 device. This feature facilitates doing worst-case designs for which data is loaded from sources which have low (or zero) minimum output propagation delays from clock edges.
MACH445-12/15/20
7
CLK0/I0 CLK1/I1
16
Clock Generator
4
CLK2/I3 CLK3/I4
C0
M0
Macrocell
M0
O0
I/O Cell
I/O0
C1
M1
Macrocell
M1
C2
M2
Macrocell
M2
O1
I/O Cell
I/O1
C3
M3
Macrocell
M3
C4
M4
Macrocell
M4
O2
I/O Cell
I/O2
C5
M5
Macrocell
M5
C6
M6
Macrocell
M6
O3
I/O Cell
I/O3
Central Switch Matrix
C7
M7
Macrocell
M7
C8
M8
Macrocell
M8
Output Switch Matrix
Logic Allocator
O4
I/O Cell
I/O4
C9
M9
Macrocell
M9
C10
M10
Macrocell
M10
O5
I/O Cell
I/O5
C11
M11
Macrocell
M11
C12
M12
Macrocell
M12
O6
I/O Cell
I/O6
C13
M13
Macrocell
M13
C14
M14
Macrocell
M14
O7
I/O Cell
I/O7
C15
M15
Macrocell
M15
17 16 24
Input Switch Matrix
16
17468E-3
Figure 1. MACH445 PAL Block 8 MACH445-12/15/20
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC +0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . -0.5 V to VCC +0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to +70C) . . . . . . . . . . . . . . . . . . . . 200 mA
OPERATING RANGES
Commercial (C) Devices Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current Test Conditions IOH = -3.2 mA, VCC = Min VIN = VIH or VIL IOL = 24 mA, VCC = Min VIN = VIH or VIL (Note 1) Guaranteed Input Logical HIGH Voltage for all Inputs (Note 2) Guaranteed Input Logical LOW Voltage for all Inputs (Note 2) VIN = 5.25 V, VCC = Max (Note 3) VIN = 0 V, VCC = Max (Note 3) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 3) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 3) VOUT = 0.5 V, VCC = Max (Note 4) VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = 5.0 V, f =25 MHz, TA = 25C (Note 5) -30 255 2.0 0.8 10 -100 10 -100 -160 Min 2.4 0.5 Typ Max Unit V V V V A A A A mA mA
CAPACITANCE (Note 6)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VIN = 2.0 V VOUT = 2.0 V VCC = 5.0 V, TA = 25C, f = 1 MHz Typ 6 8 Unit pF pF
Notes: 1. 2. 3. 4. Total IOL for one PAL block should not exceed 128 mA. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 5. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded, enabled, and reset. 6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
MACH445-12 (Com'l)
9
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)
Parameter Symbol tPD tSA -12 Parameter Description Input, I/O, or Feedback to Combinatorial Output Setup Time from Input, I/O, or Feedback to Product Term Clock Register Data Hold Time Using Product Term Clock Product Term Clock to Output Product Term, Clock Width LOW HIGH D-type T-type D-type T-type D-type T-type D-type T-type Min 3 5 6 5 4 8 8 52.6 50.0 58.8 55.6 62.5 7 8 0 2 LOW HIGH Maximum Frequency Using Global Clock (Note 2) External Feedback D-type T-type D-type Internal Feedback (f CNTS) No Feedback (Note 3) tSLA tHLA tGOA tGWA tSLS tHLS tGOS tGWS tICO Setup Time from Input, I/O, or Feedback to Product Term Clock Latch Data Hold Time Using Product Term Clock Product Term Gate to Output Product Term Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) Setup Time from Input, I/O, or Feedback to Global Gate Latch Data Hold Time Using Global Gate Gate to Output Global Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) Input Register Clock to Combinatorial Output 6 18 6 8 0 10 T-type 6 6 66.7 62.5 83.3 76.9 83.3 5 5 16 8 14 Max 12 Unit ns ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns
tHA tCOA tWLA tWHA
fMAXA
Maximum Frequency Using Product Term Clock (Note 2)
External Feedback Internal Feedback (f CNTA) No Feedback (Note 3)
tSS tHS tCOS tWLS tWHS
Setup Time from Input, I/O, or Feedback to Global Clock Register Data Hold Time Using Global Clock Global Clock to Output Global Clock Width
fMAXS
10
MACH445-12 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) (continued)
Parameter Symbol tICS tWICL tWICH fMAXIR tIGO tIGOL tIGSA tIGSS tWIGL tAR tARW tARR tAP tAPW tAPR tEA tER Input Register Clock Width Maximum Input Register Frequency 1/(t WICL + tWICH) -12 Parameter Description Input Register Clock to Output Register Setup D-type T-type LOW HIGH Min 9 10 6 6 83.3 16 18 4 9 6 16 12 10 16 12 8 2 2 12 12 Max Unit ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns
Input Latch Gate to Combinatorial Output Input Latch Gate to Output Through Transparent Output Latch Input Latch Gate to Output Latch Setup Using Product Term Output Latch Gate Input Latch Gate to Output Latch Setup Using Global Output Latch Gate Input Latch Gate Width LOW Asynchronous Reset to Registered or Latched Output Asynchronous Reset Width (Note 2) Asynchronous Reset Recovery Time (Note 2) Asynchronous Preset to Registered or Latched Output Asynchronous Preset Width (Note 2) Asynchronous Preset Recovery Time (Note 2) Input, I/O, or Feedback to Output Enable Input, I/O, or Feedback to Output Disable
Input Register with Standard-Hold-Time Option tPDL tSIR tHIR tSIL tHIL tSLLA tSLLS tPDLL Input, I/O, or Feedback to Output Through Transparent Input Latch Input Register Setup Time Input Register Hold Time Input Latch Setup Time Input Latch Hold Time Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Product Term Output Gate Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Gate Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 2 3 2 3 4 9 16 14 ns ns ns ns ns ns ns ns
MACH445-12 (Com'l)
11
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) (continued)
Parameter Symbol tPDL tSIR tHIR
-12 Parameter Description Input, I/O, or Feedback to Output Through Transparent Input Latch Input Register Setup Time Input Register Hold Time Input Latch Setup Time Input Latch Hold Time 6 0 6 0 16 18 22 Min Max 20 Unit ns ns ns ns ns ns ns ns
Input Register with Zero-Hold-Time Option
tSIL tHIL tSLLA
Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Product Term Output Gate Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Gate Input, I/O, or Feedback to Output Through Transparent Input and Output Latches
tSLLS tPDLL
Notes: 1. See Switching Test Circuit at the end of this Data Book for test conditions. 2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 3. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.
12
MACH445-12 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC +0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . -0.5 V to VCC +0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to +70C) . . . . . . . . . . . . . . . . . . . . 200 mA
OPERATING RANGES
Commercial (C) Devices Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current Test Conditions IOH = -3.2 mA, VCC = Min VIN = VIH or VIL IOL = 24 mA, VCC = Min VIN = VIH or VIL (Note 1) Guaranteed Input Logical HIGH Voltage for all Inputs (Note 2) Guaranteed Input Logical LOW Voltage for all Inputs (Note 2) VIN = 5.25 V, VCC = Max (Note 3) VIN = 0 V, VCC = Max (Note 3) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 3) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 3) VOUT = 0.5 V, VCC = Max (Note 4) VIN = 0 V, Outputs Open (IOUT = 0 mA), VCC = 5.0 V, f =25 MHz TA = 25C (Note 5) -30 255 2.0 0.8 10 -100 10 -100 -160 Min 2.4 0.5 Typ Max Unit V V V V A A A A mA mA
CAPACITANCE (Note 6)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VIN = 2.0 V VOUT = 2.0 V VCC = 5.0 V, TA = 25C, f = 1 MHz Typ 6 8 Unit pF pF
Notes: Total IOL for one PAL block should not exceed 128 mA. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 5. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded, enabled, and reset. An actual ICC value can be calculated by using the "Typical Dynamic ICC Characteristics" Chart towards the end of this data sheet. 6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 1. 2. 3. 4.
MACH445-15/20 (Com'l)
13
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)
Parameter Symbol Parameter Description tPD tSA Input, I/O, or Feedback to Combinatorial Output (Note 2) Setup Time from Input, I/O, or Feedback to Product Term Clock Register Data Hold Time Using Product Term Clock Product Term Clock to Output (Note 2) Product Term, Clock Width LOW HIGH D-type External Feedback 1/(t SA + tCOA) fMAXA Maximum Frequency Using Product Term Clock (Note 3) T-type Internal Feedback (f CNTA) No Feedback (Note 4) 1/(tWLA + tWHA) D-type T-type D-type T-type 37 47.6 45.4 55.6 10 11 0 2 LOW Global Clock Width tWHS External Feedback 1/(t fMAXS Maximum Frequency Using Global Clock (Note 3)
SS + tCOS)
-15 Min 3 D-type T-type 8 9 8 4 9 9 38.5 18 Max 15 Min 3 10 11 10 4 12 12 31.2 30.3 37 35.7 41.7 13 14 0 10 2 8 8 40 38.5 50 47.6 62.5 10 10 19 9 10 0 11 6 20 8 12 13 0
-20 Max 20 Unit ns ns ns ns 22 ns ns ns MHz MHz MHz MHz MHz ns ns ns 12 ns ns ns MHz MHz MHz MHz MHz ns ns 22 ns ns ns ns 12 ns ns 25 ns
tHA tCOA tWLA tWHA
tSS
Setup Time from Input, I/O, or Feedback to Global Clock Register Data Hold Time Using Global Clock Global Clock to Output (Note 2)
tHS tCOS tWLS
6 6 50 47.6 66.6 62.5 83.3 8 8
HIGH D-type T-type D-type Internal Feedback (f CNTS) No Feedback (Note 4) 1/(tWLS + tWHS) T-type
tSLA tHLA tGOA tGWA tSLS tHLS tGOS tGWS tICO
Setup Time from Input, I/O, or Feedback to Product Term Clock Latch Data Hold Time Using Product Term Clock Product Term Gate to Output (Note 2) Product Term Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) Setup Time from Input, I/O, or Feedback to Global Gate Latch Data Hold Time Using Global Gate Gate to Output (Note 2) Global Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) Input Register Clock to Combinatorial Output
14
MACH445-15/20 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) (continued)
Parameter Symbol Parameter Description tICS Input Register Clock to Output Register Setup D-type T-type tWICL Input Register Clock Width tWICH fMAXIR tIGO tIGOL tIGSA tIGSS tWIGL tAR tARW tARR tAP tAPW tAPR tEA tER tPDL tSIR tHIR tSIL tHIL tSLLA tSLLS tPDLL Maximum Input Register Frequency HIGH 1/(t WICL + tWICH) 6 83.3 20 22 14 16 6 20 15 15 20 15 15 2 2 15 15 17 2 4 2 4 10 12 19 2 5 2 5 12 16 24 20 20 2 2 20 20 22 20 20 25 19 21 8 25 8 62.5 25 27 ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LOW -15 Min 15 16 6 Max Min 20 21 8 -20 Max Unit ns ns ns
Input Latch Gate to Combinatorial Output Input Latch Gate to Output Through Transparent Output Latch Input Latch Gate to Output Latch Setup Using Product Term Output Latch Gate Input Latch Gate to Output Latch Setup Using Global Output Latch Gate Input Latch Gate Width LOW Asynchronous Reset to Registered or Latched Output Asynchronous Reset Width (Note 3) Asynchronous Reset Recovery Time (Note 3) Asynchronous Preset to Registered or Latched Output Asynchronous Preset Width (Note 3) Asynchronous Preset Recovery Time (Note 3) Input, I/O, or Feedback to Output Enable (Note 2) Input, I/O, or Feedback to Output Disable (Note 2)
Input Register with Standard-Hold-Time Option Input, I/O, or Feedback to Output Through Transparent Input Latch Input Register Setup Time Input Register Hold Time Input Latch Setup Time Input Latch Hold Time Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Product Term Output Gate Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Gate Input, I/O, or Feedback to Output Through Transparent Input and Output Latches
MACH445-15/20 (Com'l)
15
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) (continued)
Parameter Symbol Parameter Description Input Register with Zero-Hold-Time Option tPDL tSIR tHIR tSIL tHIL

-15 Min Max 23 6 0 6 0 16 18 25 8 0 8 0 20 24 Min
-20 Max 30 Unit ns ns ns ns ns ns ns 32 ns
Input, I/O, or Feedback to Output Through Transparent Input Latch Input Register Setup Time Input Register Hold Time Input Latch Setup Time Input Latch Hold Time Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Product Term Output Gate Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Gate Input, I/O, or Feedback to Output Through Transparent Input and Output Latches
tSLLA
tSLLS tPDLL
Notes: 1. See Switching Test Circuit at the end of this Data Book for test conditions. 2. Parameters measured with 32 outputs switching. 3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 4. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.
16
MACH445-15/20 (Com'l)
TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS
VCC = 5.0 V, TA = 25C
IOL (mA) 80 60 40 20 VOL (V) -1.0 -0.8 -0.6 -0.4 -0.2 -20 -40 -60 -80 .2 .4 .6 .8 1.0
Output, LOW
IOH (mA) 25 1 -3 -2 -1 -25 -50 -75 -100 -125 -150 2 3 4 5 VOH (V)
17468E-4
17468E-5
Output, HIGH II (mA)
20
VI (V)
-2 -1 -20 -40 -60 -80 -100 1 2 3 4 5
Input
17468E-6
MACH445-12/15/20
17
TYPICAL ICC CHARACTERISTICS VCC = 5 V, TA = 25C
325 300 275 250 225 200 175 ICC (mA) 150 125 100 75 50 25 0 0 10 20 30 40 50 60 70 MACH445
Frequency (MHz)
17468E-7
The selected "typical" pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register.
18
MACH445-12/15/20
TYPICAL THERMAL CHARACTERISTICS
Measured at 25C ambient. These parameters are not tested.
Parameter Symbol Typ Parameter Description Thermal impedance, junction to case Thermal impedance, junction to ambient Thermal impedance, junction to ambient with air flow 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air PQFP Unit C/W C/W C/W C/W C/W C/W
jc ja jma
5
38 32 28 26 24
Plastic jc Considerations
The data listed for plastic jc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the jc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment.
MACH445-12/15/20
19
SWITCHING WAVEFORMS
Input, I/O, or Feedback
VT tPD
Combinatorial Output
VT
17468E-8
Combinatorial Output
Input, I/O, or Feedback tS Clock VT tCO Registered Output
VT tH
Input, I/O, or Feedback tSL Gate tPDL VT
17468E-9
VT tHL VT tGO VT
17468E-10
Latched Out
Registered Output
Latched Output (MACH 2, 3, and 4)
tWH Clock tWL
17468E-11
Gate tGWS
VT
17468E-12
Clock Width
Gate Width (MACH 2, 3, and 4)
Registered Input tSIR Input Register Clock Combinatorial Output VT tICO
VT tHIR
Registered Input Input Register Clock VT Output Register Clock
VT
VT
tICS
VT
17468E-14
17468E-13
Registered Input (MACH 2 and 4)
Input Register to Output Register Setup (MACH 2 and 4)
Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-4 ns typical.
20
MACH445-12/15/20
SWITCHING WAVEFORMS
Latched In tSIL Gate
VT tHIL VT tIGO
Combinatorial Output
VT
17468E-15
Latched Input (MACH 2 and 4)
tPDLL Latched In Latched Out Input Latch Gate tIGOL VT
VT
tIGS Output Latch Gate
tSLL VT
17468E-16
Latched Input and Output (MACH 2, 3, and 4)
Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-4 ns typical.
MACH445-12/15/20
21
SWITCHING WAVEFORMS
tWICH Clock tWICL
17468E-17
VT
Input Latch Gate tWIGL
VT
17468E-18
Input Register Clock Width (MACH 2 and 4)
Input Latch Gate Width (MACH 2 and 4)
tARW Input, I/O, or Feedback tAR Registered Output VT tARR Clock VT
17468E-19
tAPW VT Input, I/O, or Feedback tAP Registered Output VT tAPR Clock VT
17468E-20
VT
Asynchronous Reset
Asynchronous Preset
Input, I/O, or Feedback tER Outputs VOH - 0.5V VOL + 0.5V
VT tEA VT
17468E-21
Output Disable/Enable
Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-4 ns typical.
22
MACH445-12/15/20
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
5V
S1
R1 Output R2 Test Point
CL
17468E-22
Commercial Specification tPD, tCO tEA tER S1 Closed Z H: Open Z L: Closed H Z: Open L Z: Closed 35 pF 300 5 pF 390 CL R1 R2
Measured Output Value 1.5 V 1.5 V H Z: VOH - 0.5 V L Z: VOL + 0.5 V
*Switching several outputs simultaneously should be avoided for accurate measurement.
MACH445-12/15/20
23
fMAX PARAMETERS
The parameter fMAX is the maximum clock rate at which the device is guaranteed to operate. Because the flexibility inherent in programmable logic devices offers a choice of clocked flip-flop designs, fMAX is specified for three types of synchronous designs. The first type of design is a state machine with feedback signals sent off-chip. This external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the input setup time for the external signals (tS + tCO). The reciprocal, fMAX, is the maximum frequency with external feedback or in conjunction with an equivalent speed device. This fMAX is designated "fMAX external." The second type of design is a single-chip state machine with internal feedback only. In this case, flip-flop inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the period is limited by the internal delay from the flip-flop outputs through the internal feedback and logic to the flip-flop inputs. This fMAX is designated "fMAX internal". A simple internal counter is a good example of this type of design; therefore, this parameter is sometimes called "fCNT." The third type of design is a simple data path application. In this case, input data is presented to the flip-flop and clocked through; no feedback is employed. Under these conditions, the period is limited by the sum of the data setup time and the data hold time (tS + tH). However, a lower limit for the period of each fMAX type is the minimum clock period (tWH + tWL). Usually, this minimum clock period determines the period for the third fMAX, designated "fMAX no feedback." For devices with input registers, one additional fMAX parameter is specified: fMAXIR. Because this involves no feedback, it is calculated the same way as fMAX no feedback. The minimum period will be limited either by the sum of the setup and hold times (tSIR + tHIR) or the sum of the clock widths (tWICL + tWICH). The clock widths are normally the limiting parameters, so that fMAXIR is specified as 1/(tWICL + tWICH). Note that if both input and output registers are use in the same path, the overall frequency will be limited by tICS. All frequencies except fMAX internal are calculated from other measured AC parameters. fMAX internal is measured directly.
CLK
CLK
(SECOND CHIP) LOGIC REGISTER LOGIC REGISTER
tS
t CO fMAX External; 1/(tS + tCO) CLK
tS
fMAX Internal (fCNT) CLK
LOGIC
REGISTER
REGISTER
LOGIC
tS
tSIR
tHIR fMAXIR ; 1/(tSIR + tHIR) or 1/(tWICL + tWICH)
17468E-23
fMAX No Feedback; 1/(tS + tH) or 1/(tWH + tWL)
24
MACH445-12/15/20
ENDURANCE CHARACTERISTICS
The MACH families are manufactured using our advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory.
Endurance Characteristics
Parameter Symbol Parameter Description Min 10 tDR N Min Pattern Data Retention Time Max Reprogramming Cycles 20 100 Units Years Years Cycles Test Conditions Max Storage Temperature Max Operating Temperature Normal Programming Conditions
MACH445-12/15/20
25
INPUT/OUTPUT EQUIVALENT SCHEMATICS
VCC
100 k 1 k VCC
ESD Protection
Input
VCC
VCC
100 k
1 k
Preload Circuitry
Feedback Input
17468E-24
I/O
26
MACH445-12/15/20
POWER-UP RESET
The MACH devices have been designed with the capability to reset during system power-up. Following powerup, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the
Parameter Symbol tPR tS tWL
wide range of ways VCC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met.
Parameter Descriptions Power-Up Reset Time Input or Feedback Setup Time Clock Width LOW
Max 10 See Switching Characteristics
Unit s
VCC
Power 4V
tPR
Registered Output
tS
Clock
tWL
17468E-25
Power-Up Reset Waveform
MACH445-12/15/20
27
USING PRELOAD AND OBSERVABILITY
In order to be testable, a circuit must be both controllable and observable. To achieve this, the MACH devices incorporate register preload and observability. In preload mode, each flip-flop in the MACH device can be loaded from the I/O pins, in order to perform functional testing of complex state machines. Register preload makes it possible to run a series of tests from a known starting state, or to load illegal states and test for proper recovery. This ability to control the MACH device's internal state can shorten test sequences, since it is easier to reach the state of interest. The observability function makes it possible to see the internal state of the buried registers during test by overriding each register's output enable and activating the output buffer. The values stored in output and buried registers can then be observed on the I/O pins. Without this feature, a thorough functional test would be impossible for any designs with buried registers. While the implementation of the testability features is fairly straightforward, care must be taken in certain instances to insure valid testing. One case involves asynchronous reset and preset. If the MACH registers drive asynchronous reset or preset lines and are preloaded in such a way that reset or preset are asserted, the reset or preset may remove the preloaded data. This is illustrated in Figure 2. Care should be taken when planning functional tests, so that states that will cause unexpected resets and presets are not preloaded. Another case to be aware of arises in testing combinatorial logic. When an output is configured as combinatorial, the observability feature forces the output into registered mode. When this happens, all product terms are forced to zero, which eliminates all combinatorial data. For a straight combinatorial output, the correct value will be restored after the preload or observe function, and there will be no problem. If the function implements a combinatorial latch, however, it relies on feedback to hold the correct value, as shown in Figure 3. As this value may change during the preload or observe operation, you cannot count on the data being correct after the operation. To insure valid testing in these cases, outputs that are combinatorial latches should not be tested immediately following a preload or observe sequence, but should first be restored to a known state. All MACH 2 devices support both preload and observability. Contact individual programming vendors in order to verify programmer support.
Reset Figure 3. Combinatorial Latch
17468E-27
Preloaded HIGH D Q1
Q
AR
Preloaded HIGH D Q2
Q
AR
On Preload Mode Off
Q1
AR
Q2
Figure 2. Preload/Reset Conflict
17468E-26
Set
28
MACH445-12/15/20

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